A known method for testing of electronic devices with digital circuits involves the use of scan path testing methods. Such scan path testing methods involve configuring the internal storage elements of the electronic device such that the internal storage elements can operate in two or more modes. In a first mode, the internal storage elements perform the designed task for the normal operation of the electronic device. In a second mode, the internal storage elements can be connected in a chain to produce long chains of internal storage elements in the form of a scan shift register. The first storage element in the scan shift register has its serial input connected to an input pin of the integrated circuit and the last element of the scan shift register has its serial output connected to an output pin.
The clocking signal of the internal storage elements is also arranged to be connected to a common clock line for each of the internal storage elements. The common clock line is also connected to the input pin. In the test mode, the internal storage elements can be set to any combination of logic states by scanning in a test pattern along the scan shift register from the input pin. The testing of the digital circuit is carried out in normal mode and, after performing the test, the resulting output is scanned out of the internal storage registers through an output pin for evaluation by a tester.
Many electronic devices are limited in the number of output pins and input pins. This is particularly true for the electronic devices used in automotive and sensor applications where the amount of real estate available on the chip for the inputs and outputs is substantially limited.
Typically, a scan shift interface for test purposes would require four pins: scan clock, scan in, scan shift enable and scan out. These four pins are used to control and observe the scan register chains when testing, configuring and debugging the electronic device. In a pin-limited electronic device, it is not possible to provide the four pins and there is thus a need to develop a method for communicating with the electronic device and an interface circuit to the electronic device to enable testing to take place.
The communication between the internal storage elements forming the chains of the scan shift registers needs to be synchronous and thus the data stream in the form of test patterns needs to be applied coherently to the electronic device.
It is known that the length of the chain of the shift scan register is arbitrary and will depend on the number of internal storage registers available. It is therefore, in many cases, not possible to apply a test pattern of standard length to the electronic device and means have to be provided to cater for such irregular lengths of test patterns. There is therefore also a need for a scan_shift_enable signal to be encoded at the start of a data stream in which the test patterns are shifted into the scan shift register. The use of the scan_shift_enable signal enables the serial application of the scanned input data for the test patters as well as capture of the responses of the electronic device and scanning out of the responses.
As mentioned above, the current art for scanning in test patterns requires four pins. Current known serial interface circuits for the electronic devices with a low number of pins, i.e. fewer than four pins, require fixed baud rates or RF encoding with framing conventions used for fixed length data sequences. Such serial interface circuits are complex and carry a large implementation overhead on the chip, as well as being unsuitable for use with scan shift data, such as that used for the testing.
U.S. Pat. No. 8,443,125 (Beccue, assigned to Analog Devices), teaches a method for communication between two devices using a single pin. The method includes combining a data stream and a clock signal to form a three-voltage level data stream. The third voltage level records the transitions of the clock while the serial data is either high or low. This is achieved by using the first voltage level and the second voltage level when the serial clock is low and the serial data is respectively high or low and the third voltage level when the serial clock is high, so that transitions of the serial clock are present in the combined data stream. The protocol described in this patent provides a simple way for transmitting data and a clock signal between two devices over a single wire. It fails to teach, however, how this system could be applied to scanning test patterns into an electronic device to be tested.
U.S. Pat. No. 7,770,812 (Merk, assigned to Texas Instruments) describes an interface system for a single logic input pin of an electronic system. The interface system includes a decoder for converting a pulse coded signal applied to the logic input pin to a sequence of logic low and logic high values, as well as a state machine which is responsive to the sequence of logic values to switch the electronic system between different modes of operation. The interface can be used to scan programming data into the electronic system.
Another interface circuit for a single pin is known from U.S. Patent Application Publication No. 2006/0087307 (De Winter).